It is conventional for a Serializer/Deserializer (SerDes) receiver to detect not only high-speed serial data but to also detect various side-band lower frequency signals. To do so, the SerDes receiver may include a frequency detector to distinguish between the high-speed data and the sideband signals. For example, a frequency detection filter such as an LC filter or RC filter may be used to perform this detection. However, the definition of “low frequency” with regard to distinguishing the side-band signals from the high-speed data depends upon the standard and varies widely. Therefore, a third order or even higher filter design may be required to accommodate such a variable frequency cutoff between the sideband signaling and the high-speed serial data. But multiple-pole LC filters are bulky and impractical. Similarly, RC filters also demand significant die space and consume substantial amounts of power. Alternatively, oversampling circuits may be used but such circuits are also bulky and power-intensive as the distinction between the side-band signaling and the high-speed data is pushed into the higher frequencies such as in the PCIE standard.
In addition, the voltage levels (signal amplitudes) are also variable depending upon the particular standard being implemented. A modern SerDes receiver may need to accommodate input signal amplitude variations of more than five times in some cases. Low-frequency, small-amplitude signals must pass through the same frequency detection filter in such a receiver as do high-frequency, large-amplitude signals. This amplitude variation further complicates the design of multi-pole frequency detection filters such as RC filters.
Accordingly, there is a need in the art for systems and methods for improved frequency detection.